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- W2889884085 abstract "A new SRAM cell with better leakage control and enhanced memory retention capability is proposed. The memory array configured using the proposed SRAM cell has all its word lines and bit lines driven adiabatically using differential cascode and pre-resolved adiabatic logic (DCPAL), and it operates as a buffer for the memory array. This paper demonstrates how one of major concerns, namely, the VT variation can be controlled by modifying the ground-line and power-line voltage of the SRAM cell. The designs are implemented using 45-nm technology models operating at a supply voltage of 0.8 V." @default.
- W2889884085 created "2018-09-27" @default.
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- W2889884085 date "2018-09-15" @default.
- W2889884085 modified "2023-09-25" @default.
- W2889884085 title "Adiabatic SRAM Cell and Array" @default.
- W2889884085 cites W2029286699 @default.
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- W2889884085 doi "https://doi.org/10.1007/978-981-10-8797-4_38" @default.
- W2889884085 hasPublicationYear "2018" @default.
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