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• W2889968143 abstract "Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses." @default.
• W2889968143 created "2018-09-27" @default.
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• W2889968143 date "2018-10-04" @default.
• W2889968143 modified "2023-10-03" @default.
• W2889968143 title "Channel characterization for chip-scale wireless communications within computing packages" @default.
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• W2889968143 doi "https://doi.org/10.5555/3306619.3306639" @default.
• W2889968143 hasPublicationYear "2018" @default.
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