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• W2889987629 abstract "Silicon carbide (SiC) power modules are promising for high-power applications because of the high breakdown voltage, high operation temperature, low ON-resistance, and fast switching speed. However, the large parasitic inductance in existing package designs results in compromised performance, i.e., long blanking time in the desaturation protection scheme and large overvoltage spikes during the switching transient. Consequently, the benefits of SiC devices are often not fully utilized in practical applications. This paper deals with these two issues and aims at improving the electrical performance of the existing SiC module package. Specifically, a package design with Kelvin drain-to-source connection is first proposed to minimize the blanking time. More than 99% reduction of blanking time is achieved experimentally compared to the conventional package design. Second, a low parasitic inductance package with double-side cooling is proposed to allow the fast switching speed of SiC devices without sacrificing the thermal performance. A power loop inductance of 1.63 nH is realized from Q3D simulation. Verified by the experiment, more than 60% reduction of power loop inductance is achieved in comparison to a previously designed baseline module. At 0- $Omega $ external gate resistance, the turn-off voltage spike is less than 9% of the dc-link voltage under the rated load condition." @default.
• W2889987629 created "2018-09-27" @default.
• W2889987629 creator A5001340491 @default.
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• W2889987629 date "2019-03-01" @default.
• W2889987629 modified "2023-10-17" @default.
• W2889987629 title "Electrical Performance Advancement in SiC Power Module Package Design With Kelvin Drain Connection and Low Parasitic Inductance" @default.
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• W2889987629 doi "https://doi.org/10.1109/jestpe.2018.2870248" @default.
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