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- W2890575105 abstract "The demand increasing for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. Binary addition is the most basic operation found in arithmetic components. The most basic arithmetic operation is addition and the most fundamental arithmetic component of the processor is an adder. Transistor count is a primary concern which largely affects the design complexity of many function units such as multiplier and algorithmic logic unit (ALU). In application such as Digital Signal Processing (DSP) architecture, microprocessor, microcontroller and data processing units, Full adder is an important component In the next generation processors, fundamental computation units should be incorporated with a design, such as multipliers. The characterization and optimization of such multipliers will depend on the comparison and choice of multiplier modules in system design. This indicates a need to design multipliers towards the development of power-efficient high performance systems. To achieve higher processing speeds, parallel multipliers are usually adopted at the expense of high area optimization. This paper gives a comparison for the performance of different Full adder cells based on their transistor count and uses architecture of 4-bit and 8-bit Braun multiplier for the successful implementation of layouts using cadence tool for 180nm technology." @default.
- W2890575105 created "2018-09-27" @default.
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- W2890575105 date "2017-09-01" @default.
- W2890575105 modified "2023-09-26" @default.
- W2890575105 title "VLSI Implementation of Braun Multiplier using Full Adder" @default.
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- W2890575105 doi "https://doi.org/10.1109/ctceec.2017.8455157" @default.
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