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- W2891290919 abstract "The QR decomposition (QRD) is an important prerequisite for many different applications such as multiple input multiple output (MIMO) detection in wireless communication system, matrix inversion, radar application and so on. This paper presents the design and implementation of a 32-bit MIPS (Microprocessor without Interlocked Pipeline Stage) processor based on QRD using Givens Rotation algorithm. Moreover, this design contains a developed hardware in order to reduce the latency of QRD process. The implementation results of this QRD processor are compared with another work. Finally, design, synthesis of this QRD processor has been achieved using Xilinx 14.7 ISE simulator and coding is written in Verilog HDL language and implemented on Virtex - 7 FPGA (Field Programmable Gate Array) kit." @default.
- W2891290919 created "2018-09-27" @default.
- W2891290919 creator A5006953438 @default.
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- W2891290919 date "2018-05-01" @default.
- W2891290919 modified "2023-09-27" @default.
- W2891290919 title "Design and implementation of 32-Bits MIPS processor to Perform QRD Based on FPGA" @default.
- W2891290919 cites W1992472739 @default.
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- W2891290919 doi "https://doi.org/10.1109/iiceta.2018.8458073" @default.
- W2891290919 hasPublicationYear "2018" @default.
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