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- W2891324562 abstract "Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Previous work has focused on achieving efficient mapping of GPCs on FPGAs by using a combination of general Look-up table (LUT) fabric and specialized fast carry chains. The resulting structures are purely combinational and cannot be efficiently pipelined to achieve the potential FPGA performance. In this paper, we take an alternate approach and try to eliminate the fast carry chain from the GPC structure. We present a heuristic that maps GPCs on FPGAS using only general LUT fabric. The resultant GPCs are then easily re-timed by placing registers at the fan-out nodes of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry chain from the GPC structure with the same LUT count in most of the cases. Experimental results using Xilinx Kintex-7 FPGAs show a considerable reduction in critical path and dynamic power dissipation with same area utilization in most of the cases." @default.
- W2891324562 created "2018-09-27" @default.
- W2891324562 creator A5056808073 @default.
- W2891324562 date "2017-07-14" @default.
- W2891324562 modified "2023-10-04" @default.
- W2891324562 title "LUT Based Generalized Parallel Counters for State - of - art FPGAs" @default.
- W2891324562 doi "https://doi.org/10.7251/els1721003k" @default.
- W2891324562 hasPublicationYear "2017" @default.
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