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• W2892907636 abstract "Summary In this study, we propose a robust field‐programmable gate array (FPGA)–based time‐to‐digital converter (TDC) with run‐time calibration. A code density test was used for differential nonlinearity (DNL) calibration to deal with nonuniformity in delay cells. The proposed calibration scheme is implemented as a four‐step finite state machine (FSM) for run‐time calibration. We implemented the TDC with the proposed run‐time calibration circuit on the Xilinx 65‐nm FPGA platform. This improved the DNL and integral nonlinearity (INL) values over those obtained using a TDC without run‐time calibration circuit. The DNL and INL values at a time resolution of 46.875 picoseconds were [−0.68, 1.04] and [−4.27, 2.27] least significant bits, respectively. More than 30% DNL and INL improvements are achieved for the TDC with calibration circuit. The results obtained at temperatures of 27°C to approximately 70°C indicated that the proposed run‐time calibration circuit enhanced the capability of the FPGA‐based TDC against temperature effects. The FPGA‐based TDC with the proposed run‐time calibration FSM provides robust high‐resolution performance suited for a range of scientific applications." @default.
• W2892907636 created "2018-10-05" @default.
• W2892907636 creator A5059884632 @default.
• W2892907636 date "2018-09-27" @default.
• W2892907636 modified "2023-10-14" @default.
• W2892907636 title "Run-time calibration scheme for the implementation of a robust field-programmable gate array-based time-to-digital converter" @default.
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• W2892907636 doi "https://doi.org/10.1002/cta.2571" @default.
• W2892907636 hasPublicationYear "2018" @default.
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