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• W2893267240 abstract "We propose an algorithmic voltage-feed-in (AVFI) topology capable of systematic generation of any arbitrary buck-boost rational ratio with optimal conduction loss while achieving reduced topology-level parasitic loss among the state-of-the-art works. By disengaging the existing topology-level restrictions, we develop a cell-level implementation using the extracted Dickson cell (DSC) and charge-path-folding cell (QFC) to minimize the power-stage parasitic loss, exhibiting a Dickson-like switching pattern. The proposed partitionable main cell (MC) and auxiliary cell (AC) architecture achieves fined-grained voltage conversion ratio (FVCR) reconfiguration with optimal power cell utilization and reduced control complexity. Implemented in 65-nm bulk CMOS, the fully integrated switched-capacitor power converter (SCPC) using 10 MCs and 10 ACs executes a total of 24 VCRs (11 buck and 13 boost) with wide-range efficient buck-boost operations through the proposed reference-selective bootstrapping driver (RSBD). Based on the AVFI topology, the chip prototype reaches a measured peak efficiency of 84.1% at a power density of 13.4 mW/mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> over a wide range of input (0.22-2.4 V) and output (0.85-1.2 V)." @default.
• W2893267240 created "2018-10-05" @default.
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• W2893267240 date "2018-12-01" @default.
• W2893267240 modified "2023-10-17" @default.
• W2893267240 title "Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck–Boost Switched-Capacitor DC–DC Converters" @default.
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• W2893267240 doi "https://doi.org/10.1109/jssc.2018.2866929" @default.
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