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• W2893533083 abstract "In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm2. Post layout simulations show better performance compared with other reported techniques." @default.
• W2893533083 created "2018-10-05" @default.
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• W2893533083 date "2018-11-01" @default.
• W2893533083 modified "2023-10-18" @default.
• W2893533083 title "A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications" @default.
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• W2893533083 doi "https://doi.org/10.1016/j.aeue.2018.09.036" @default.
• W2893533083 hasPublicationYear "2018" @default.
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