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- W2894460419 abstract "A wideband static frequency divider was designed in a standard SiGe BiCMOS technology in the paper. The flip-flop structure was used in the circuit design. The divider is implemented in current-mode logic (CML) structure. The input frequency range is from 0.1 GHz to 20 GHz for divider ratios of 8. The phase noise can achieve to be −147 dBc/Hz at 100 kHz offset for the input frequency of 20 GHz. The ouput power is about - 3dBm in the operating frequency range. The divider works at a supply voltage of 5 V with a power consumption of less than 400 mW." @default.
- W2894460419 created "2018-10-05" @default.
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- W2894460419 date "2018-05-01" @default.
- W2894460419 modified "2023-10-11" @default.
- W2894460419 title "The Design of a Wideband Static Frequency Divider" @default.
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- W2894460419 doi "https://doi.org/10.1109/imcec.2018.8469515" @default.
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