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- W2895549242 abstract "In this paper, two novel methods to design a high speed, low power 16-Tap 32-bit digital FIR filter for DSP application are proposed. The basic building blocks of the FIR filters are adders, multipliers and delay elements. In the proposed work, proposed filter-1 is designed using carry increment adder and 32-bit Vedic multiplier and proposed filter-2 is designed using altered carry skip adder and 32-bit Vedic multiplier. FIR filter architectures with 16-TAP is developed using Verilog HDL and implemented using 45qm technology. The ASIC result shows the proposed-1 and proposed-2 16-TAP 32-bit filter has power dissipation of 7.36mW and 7.282mW with the delay of 6.79ηS and 7.23ηS respectively." @default.
- W2895549242 created "2018-10-12" @default.
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- W2895549242 date "2018-02-01" @default.
- W2895549242 modified "2023-09-25" @default.
- W2895549242 title "Design and implementation of 16 tap FIR filter for DSP Applications" @default.
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- W2895549242 doi "https://doi.org/10.1109/icaecc.2018.8479480" @default.
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