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- W2896035949 abstract "A test setup is developed, measured, and modeled to examine the insertion loss effects of Electroless-Nickel Immersion-Gold (ENIG) plating on various PCB topologies from 1 to 50 GHz. ENIG plating is observed to increase insertion loss compared with unplated samples nonlinearly in a manner that generally increases with frequency. Three main topolgies are analyzed; a 0.005 (0.127 mm) thick microstrip circuit using RT/duroid® 6002 laminate, a 0.008 (0.203 mm) thick microstrip using RO4003C™ laminate, and a 0.008 (0.203 mm) thick Grounded Co-Planar Waveguide (GCPW) using RO4003C™ laminate." @default.
- W2896035949 created "2018-10-26" @default.
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- W2896035949 date "2018-08-01" @default.
- W2896035949 modified "2023-09-24" @default.
- W2896035949 title "An Efficient EM Simulation Model for ENIG Plated Metal Finishes Including Conductor Side-Wall Plating Verified With Physical Measurement from 1 to 50 GHz" @default.
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- W2896035949 doi "https://doi.org/10.1109/imws-5g.2018.8484386" @default.
- W2896035949 hasPublicationYear "2018" @default.
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