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- W2896775487 abstract "Approximate computing permits compromise on the accuracy of output of computational circuits to reduce the area of these circuits and lessen their power consumption. However, the acceptability of inexact output is an application specific phenomenon. In this paper, we particularly address the case of multiplier design such that features of accuracy and low area/power are equally sought, by proposing CMOS/Pass Transistor Logic (PTL) based approximate multiplier (MCPAM). MCPAM is a transistor level 2 by 2 novel approximate multiplier with minimum error distance and compact architecture. In case of applications with exact output requirements, MCPAM can be configured for accuracy through a proposed low-cost error detection and correction mechanism. The novelty of the method lies in the design of approximate multiplier that is to use static CMOS style and PTL logic together for low area/power design implementation. Experimental results and comparative analysis using 45nm demonstrate 60% to 83.6% and 71.3% improvement in power and area, respectively, as compared with previously proposed approximate multiplier. When MCPAM is used in conjunction with its error detection and correction unit, up to 37.4% and 17.3% reduction in area and power consumption, respectively, is observed as compared with previously proposed approximate multiplier employing error correction." @default.
- W2896775487 created "2018-10-26" @default.
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- W2896775487 date "2018-08-01" @default.
- W2896775487 modified "2023-09-26" @default.
- W2896775487 title "Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTL" @default.
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- W2896775487 doi "https://doi.org/10.1109/dsd.2018.00045" @default.
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