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• W2897049914 abstract "With continuous scaling of technology, density of transistor is increasing which leads to higher power dissipation on the chip. Therefore the need of the hour is to reduce the power consumption of individual circuits. In this paper a new mixed logic of TGL and DVL a power efficient circuit is proposed. The proposed adder is operated at 0.9V supply with $mathbf{1.894} mu mathbf{W}$ in 90 nm NG-spice CMOS process technology." @default.
• W2897049914 created "2018-10-26" @default.
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• W2897049914 date "2018-03-01" @default.
• W2897049914 modified "2023-09-24" @default.
• W2897049914 title "Analysis of Power Reduction Techniques in Digital Circuits in Submicron Regime" @default.
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• W2897049914 doi "https://doi.org/10.1109/iceca.2018.8474870" @default.
• W2897049914 hasPublicationYear "2018" @default.
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