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- W2897480454 abstract "We propose and experimentally demonstrate double-gated n-type WSe <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> FETs with excellent top gate high-k dielectric layer. Under back gate control, the devices behave as n-type enhancement transistors, with ON/OFF current ratios larger than 6 orders of magnitude and a ON current close to 1 pA/μm under a drain bias of 100 mV. Negative top gate biases determine a much steeper turn-on of the back gated transfer characteristic and a reduction of the hysteresis. Top gated device behaves as n-type depletion FETs, exhibiting a I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>ON</sub> /I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>OFF</sub> ratio larger than 10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>6</sup> under positive bias applied to the back gate. A minimum hysteresis of 40 mV and an average subthreshold slope close to 100 mV/dec prove the high quality of the deposited top gate dielectric. The electron mobility has been extracted using the Y-function method, obtaining 22.15 cm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> V <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-1</sup> s <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-1</sup> under a drain bias of 1 mV." @default.
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- W2897480454 date "2018-09-01" @default.
- W2897480454 modified "2023-10-18" @default.
- W2897480454 title "Double gate n-type WSe2 FETs with high-k top gate dielectric and enhanced electrostatic control" @default.
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- W2897480454 doi "https://doi.org/10.1109/essderc.2018.8486867" @default.
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