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• W2897546404 abstract "With the increase in number and complexity of cores and components in CMPs and SoCs, a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network on Chips(NoC) emerged as the reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. In this paper, we explore the design space of 3D NoCs using floorplan driven wire lengths and link delay estimation. We analyse the performance and cost of 2D and two 3D variants of the Mesh topology by injecting two synthetic traffic pattern for varying buffer space and floorplan based delays were considered to for the experiments. Results of our experiments show that for the injection rates from 0.02 to 0.2 the average network latency of a 4layer 3D Mesh is reduced up to 54% compared to its 2D counterpart. The on chip communication performance improved up to 2.2× and 3.1× in 4-layer 3D Mesh compare to 2D Mesh with uniform and transpose traffic patterns respectively." @default.
• W2897546404 created "2018-10-26" @default.
• W2897546404 creator A5004440264 @default.
• W2897546404 creator A5053833898 @default.
• W2897546404 date "2018-03-01" @default.
• W2897546404 modified "2023-09-26" @default.
• W2897546404 title "Accurate Performance Analysis of 3D Mesh Network on Chip Architectures" @default.
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• W2897546404 doi "https://doi.org/10.1109/conecct.2018.8482383" @default.
• W2897546404 hasPublicationYear "2018" @default.
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