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- W2898778885 abstract "In this research paper we represented the design and evaluation of 8:1 Multiplexer using different adiabatic logics. For VLSI design engineers, high power consumption is the main factor in digital circuits. In this paper we are going to presents the CMOS-logic based new design in 90 nm technology for a low power and high speed adiabatic 8:1 Multiplexer and De-Multiplexer for following this trend. In which we focus on the characteristics of the CMOS and adiabatic logic families 2N2P, 2N-2N2P use a cross-coupled transistor structure for adiabatic operation and dual sleep approach. Normally Adiabatic logic families use multiphase clocks. Multiphase clock increases power dissipation on their clock distribution network. Some adiabatic logics are not effective for high speed operating design due to their clock skew issues and high complexity because of multiphase clocks. So in this research paper we are focusing on energy recovery with efficient power clock power consumption." @default.
- W2898778885 created "2018-11-09" @default.
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- W2898778885 date "2018-07-01" @default.
- W2898778885 modified "2023-09-25" @default.
- W2898778885 title "Designing of Multiplexer and De-Multiplexer Using Different Adiabatic Logic in 90nm Technology" @default.
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- W2898778885 doi "https://doi.org/10.1109/icccnt.2018.8494170" @default.
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