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• W2898845331 abstract "This paper theorizes the possibilities of generalizing a memristor based ternary adder circuit, to a memristor based multi-valued logic adder. The proposition tries to achieve the theoretical advantages of processing different numbering systems, increasing the density, and decreasing the processing time, by utilizing the memristor properties and dynamics. This is done using a memristor cell based circuit structure. The memristor is quantized to more levels in order to accommodate more values of logic being processed. Quinary numbering system is used to demonstrate the generalization, then a process of generalization is shown. Circuit modifications can be made to process different numbering systems." @default.
• W2898845331 created "2018-11-09" @default.
• W2898845331 creator A5012912231 @default.
• W2898845331 creator A5069997789 @default.
• W2898845331 date "2019-01-01" @default.
• W2898845331 modified "2023-09-23" @default.
• W2898845331 title "Memristor-based quinary half adder" @default.
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• W2898845331 doi "https://doi.org/10.1016/j.aeue.2018.10.033" @default.
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