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• W2898857372 abstract "A power-efficient pipeline analog-to-digital converter (ADC) architecture employing a current-mode (CM) multiplying digital-to-analog converter (MDAC) is implemented in this paper. A linear operational transconductance amplifier (OTA), a current steering DAC, and a transimpedance amplifier (TIA) work together as an error amplifier to implement the first stage of the pipeline ADC. The high output impedance displayed by both OTA and MDAC allow us to maximize the power efficiency of the residue amplifier. Compared with a conventional switched-capacitor (SC) MDAC architecture, the proposed CM MDAC reduces the architecture's power consumption. The fabricated pipeline ADC achieves a 61.3-dB/60.2-dB signal-to-noise and distortion ratio (SNDR) and a 76-dB/74-dB spurious-free dynamic range (SFDR) for a sinusoidal input of 4.15 and 97.9 MHz, respectively. The ADC's power consumption when operating at 200 MS/s is 8.4 mW, and the conversion figure of merit (FoM) is a 44 fJ/conversion step. The prototype occupies an active area of 0.23 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> in a mainstream low-power 40-nm CMOS technology." @default.
• W2898857372 created "2018-11-09" @default.
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• W2898857372 date "2018-11-01" @default.
• W2898857372 modified "2023-09-26" @default.
• W2898857372 title "A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs" @default.
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• W2898857372 doi "https://doi.org/10.1109/jssc.2018.2863959" @default.
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