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- W2899024237 abstract "Multipliers are the most vital blocks in many digital applications, i.e. digital filters, Digital Signal Processors (DSPs). Further, multipliers are considered as crucial elements in Floating Point(FP) arithmetic operations which are widely used in the real time signal processing applications. The design of FP multiplier is relatively complex than integer multipliers. In floating point multiplication so far, many multiplier designs like array, Wallace and booth are embedded to improve the performance of the design. From the literature, it is inferred that no multiplier design provides satisfied performance with respect to all important performance metrics such as area, delay and power. Hence, in this paper, the design and analysis of single precision floating point multiplication with Vedic multiplier is presented by considering modified 2×1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing multiplier techniques. To achieve further improvement in the performance of single precision floating point multiplication with Vedic multiplier, Canonic Signed Digit CSD technique is incorporated in that floating-point multiplication to improve the hardware efficiency by using minimum number of adders (or subtractor) blocks. Moreover, this paper examines the optimized design methods of CSD multipliers by using different techniques which are used in the above-mentioned multiplier using Vedic. Further, the performance analysis of single precision floating point multiplier using Vedic and CSD is analyzed in terms of area and delay and also compared with that of different existing techniques. From the simulation results, it is observed that single precision floating point multiplication with CSD multiplier gives better performance than the floating-point multiplier using Vedic with and without modified techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator." @default.
- W2899024237 created "2018-11-09" @default.
- W2899024237 creator A5055979687 @default.
- W2899024237 creator A5064731351 @default.
- W2899024237 date "2018-07-01" @default.
- W2899024237 modified "2023-09-28" @default.
- W2899024237 title "Implementation and Analysis of Single Precision Floating Point Multiplication Using Vedic and Canonic Signed Digit Algorithm" @default.
- W2899024237 cites W1506055705 @default.
- W2899024237 cites W1969291996 @default.
- W2899024237 cites W1975189549 @default.
- W2899024237 cites W2031931186 @default.
- W2899024237 cites W2056410596 @default.
- W2899024237 cites W2074224805 @default.
- W2899024237 cites W2087898301 @default.
- W2899024237 cites W2136001068 @default.
- W2899024237 cites W2158793378 @default.
- W2899024237 cites W2291254403 @default.
- W2899024237 cites W2543648414 @default.
- W2899024237 doi "https://doi.org/10.1109/icccnt.2018.8494184" @default.
- W2899024237 hasPublicationYear "2018" @default.
- W2899024237 type Work @default.
- W2899024237 sameAs 2899024237 @default.
- W2899024237 citedByCount "1" @default.
- W2899024237 countsByYear W28990242372022 @default.
- W2899024237 crossrefType "proceedings-article" @default.
- W2899024237 hasAuthorship W2899024237A5055979687 @default.
- W2899024237 hasAuthorship W2899024237A5064731351 @default.
- W2899024237 hasConcept C11413529 @default.
- W2899024237 hasConcept C114614502 @default.
- W2899024237 hasConcept C173608175 @default.
- W2899024237 hasConcept C201290732 @default.
- W2899024237 hasConcept C2524010 @default.
- W2899024237 hasConcept C2780595030 @default.
- W2899024237 hasConcept C28719098 @default.
- W2899024237 hasConcept C33923547 @default.
- W2899024237 hasConcept C35912277 @default.
- W2899024237 hasConcept C41008148 @default.
- W2899024237 hasConcept C48372109 @default.
- W2899024237 hasConcept C84211073 @default.
- W2899024237 hasConcept C94375191 @default.
- W2899024237 hasConcept C94957134 @default.
- W2899024237 hasConceptScore W2899024237C11413529 @default.
- W2899024237 hasConceptScore W2899024237C114614502 @default.
- W2899024237 hasConceptScore W2899024237C173608175 @default.
- W2899024237 hasConceptScore W2899024237C201290732 @default.
- W2899024237 hasConceptScore W2899024237C2524010 @default.
- W2899024237 hasConceptScore W2899024237C2780595030 @default.
- W2899024237 hasConceptScore W2899024237C28719098 @default.
- W2899024237 hasConceptScore W2899024237C33923547 @default.
- W2899024237 hasConceptScore W2899024237C35912277 @default.
- W2899024237 hasConceptScore W2899024237C41008148 @default.
- W2899024237 hasConceptScore W2899024237C48372109 @default.
- W2899024237 hasConceptScore W2899024237C84211073 @default.
- W2899024237 hasConceptScore W2899024237C94375191 @default.
- W2899024237 hasConceptScore W2899024237C94957134 @default.
- W2899024237 hasLocation W28990242371 @default.
- W2899024237 hasOpenAccess W2899024237 @default.
- W2899024237 hasPrimaryLocation W28990242371 @default.
- W2899024237 hasRelatedWork W2016265800 @default.
- W2899024237 hasRelatedWork W2027894739 @default.
- W2899024237 hasRelatedWork W2127257608 @default.
- W2899024237 hasRelatedWork W2169016399 @default.
- W2899024237 hasRelatedWork W2264007019 @default.
- W2899024237 hasRelatedWork W2733078922 @default.
- W2899024237 hasRelatedWork W2896390749 @default.
- W2899024237 hasRelatedWork W3089760653 @default.
- W2899024237 hasRelatedWork W4308076430 @default.
- W2899024237 hasRelatedWork W2181666672 @default.
- W2899024237 isParatext "false" @default.
- W2899024237 isRetracted "false" @default.
- W2899024237 magId "2899024237" @default.
- W2899024237 workType "article" @default.