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- W2899092733 abstract "A full-rate CDR loop employs a 3-stage ring VCO, a master-slave passive sampler as both a phase detector and a filter, and a new flipflop to achieve a bandwidth of 170 MHz. Implemented in 45-nm CMOS technology, the circuit exhibits a jitter tolerance of 2 UI at 5 MHz and a recovered clock jitter of 340 fs with $2^{7}-1$ PRBS." @default.
- W2899092733 created "2018-11-09" @default.
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- W2899092733 date "2018-06-01" @default.
- W2899092733 modified "2023-09-22" @default.
- W2899092733 title "A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance" @default.
- W2899092733 doi "https://doi.org/10.1109/vlsic.2018.8502278" @default.
- W2899092733 hasPublicationYear "2018" @default.
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