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• W2899297761 startingPage "2205" @default.
• W2899297761 abstract "CMOS downscaling poses a growing concern for circuit lifetime reliability. Bias temperature instability (BTI) is a major source of transistor aging, causing a threshold voltage increase in CMOS devices, and affecting circuit timing. This paper presents an aging mitigation approach that can be incorporated into standard synthesis. We propose a technique to restructure the logic expressions for aging-critical gates and to reduce the BTI stress duty cycle. A new technology mapping strategy is demonstrated, including a forward pass to select the most suitable cells and implement the optimized logic, and a backward pass to validate remapped circuits by restricting the negative slacks. The negative slacks produced in the mapping stage are eliminated by gate-level optimization, which aims to optimize a circuit to improve lifetime reliability under timing and area constraints. It employs a sensitivity metric that can be adjusted according to the design specifications to pick the most favorable transformation in terms of timing, lifetime or both. Our results show a 59.1% lifetime improvement with 0.86% area overhead on average. Compared with conventional over-design, a 28.29% higher lifetime improvement is realized. In addition, our approach can optimize a circuit under each corner case, considering both process variations and input data." @default.
• W2899297761 created "2018-11-09" @default.
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• W2899297761 date "2018-11-01" @default.
• W2899297761 modified "2023-09-27" @default.
• W2899297761 title "Lifetime Reliability-Aware Digital Synthesis" @default.
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• W2899297761 doi "https://doi.org/10.1109/tvlsi.2018.2861820" @default.
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