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- W2900026400 abstract "A novel defect-tolerant network of digital-to-analog converters (DACs) is presented in this paper. The architecture of this converter employs a single 2.5-V voltage reference and an unbalanced buffering technique to achieve a wide voltage range that extends from 864 mV to 2.538 V with an 8-bit resolution. The proposed converter incorporates a defect-tolerant architecture and is extremely compact, utilizing a per-bit silicon area of less than 350 μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . Although such very small area allows for embedding in dense configurable fabrics (field-programmable gate arrays) and wafer-scale integration, the overall performance is not sacrificed as reported measurements show a signal-tonoise ratio of 51.87 dB and a spurious-free dynamic range of 42.31 dB, at 10 MS/s providing 7.6 effective bits. Moreover, the proposed architecture benefits from dynamic calibration capabilities, as any converter output can be finely adjusted over a range of 25 mV. This proposed DAC is also extensively reused in the same defect-tolerant network for a successive approximation register-analog-to-digital converter, as well as for a configurable voltage reference." @default.
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- W2900026400 date "2019-02-01" @default.
- W2900026400 modified "2023-09-23" @default.
- W2900026400 title "A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration" @default.
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- W2900026400 doi "https://doi.org/10.1109/tvlsi.2018.2876458" @default.
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