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• W2900339054 abstract "This brief presents a novel pipelined algorithm for transposing an ${N times N}$ matrix, as well as a modular architecture for this algorithm. The architecture is optimal in both memory, using the minimum number of registers necessary to transpose an ${N times N}$ matrix, and latency, achieving the theoretical minimum. The architecture is composed of a series of identical cascaded basic circuits and has a simple control strategy. Furthermore, the algorithm and architecture can be easily extended to ${p}$ –parallel where ${p}$ is any factor of ${N}$ ." @default.
• W2900339054 created "2018-11-16" @default.
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• W2900339054 date "2019-04-01" @default.
• W2900339054 modified "2023-10-11" @default.
• W2900339054 title "Pipelined Algorithm and Modular Architecture for Matrix Transposition" @default.
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• W2900339054 doi "https://doi.org/10.1109/tcsii.2018.2880437" @default.
• W2900339054 hasPublicationYear "2019" @default.
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