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• W2903568400 abstract "Abstract Moore's Law has been through many challenges in the last few years. The transistors continued to shrink to smaller sizes but the benefit of better performance and lower cost that comes along with shrinking is facing difficulties. Semiconductor industries are trying to come up with new ways to keep the Moore's Law going on two different fronts: where foundries are working on more Moore solutions and packaging houses are working on more than Moore solutions. Recently the industry has been considering the chip splitting and re-constitution in the form of SiP which has relatively shorter development time and lower cost than the SoC. But traditional SiP with wirebonding or FC connections to substrate will lead to high transmission loss and power consumption. A new fine line SiP solution is required to shorten the connection between chips to improve the performance. Different from the 3DIC and 2.5DIC technologies, fine line panel level fan out has the advantages of good performance, design flexibility, and high production efficiency. This paper will discuss about the challenges in setting up this technology including establishing standards, tools preparation, and process difficulties. The dedicated machines that handle the fine line panel level fan out are critical. It is not easy to select suitable tools for this new technology. We also need to co-develop with tool vendors for some process stages which suitable tools from existing industries could not be easily found. Additionally, panel warpage and chip shift are two of major process challenges. Experiences on overcoming these difficulties will be shared. Different structures and processes have been developed for varied application requirements. The chip first approach encapsulates chips and then build RDL layers on the encapsulation surface. It is suitable for mobile AP, baseband, ASIC, PMIC, and memory. The chip last solution build RDL first, then flip chip mounting the bumped chips on the RDL. The RDL can be tested before the mounting of chips. It is suitable for CPU, GPU, FPGA, and thermal sensitive devices. Pillars in fan out is a chip middle solution. It uses Cu pillars to connect top and bottom RDLs which is good for chip stacking. Currently the 5/5um line/space is already been qualified. 3/3um under development and tool capability is 2/2um. Several real cases will be demonstrated in this paper to help the readers understand this technology. This technology is expected to be crucial for the coming era of 5G, automotive, IoT, and AI. It is believed that this technology can be applied to different kinds of end applications. For example, multi-chip stacking in a fan out package to achieve high bandwidth performance. Fan out stacking of logic and memory chips which can replace the existing PoP. Using fan out to integrate passives and/or other chips can achieve a compact SiP. Fan out could be one of the embedded substrate. Fan out RDL process can also be a suitable platform for antenna in package designs. This paper will introduce the challenges of Moore's law as beginning, and then explain the advantages and the challenges of fine line panel fan out technology, and the proposed approaches to address those challenges." @default.
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• W2903568400 date "2018-10-01" @default.
• W2903568400 modified "2023-10-14" @default.
• W2903568400 title "Fine line panel level fan out changes the SiP landscape" @default.
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• W2903568400 doi "https://doi.org/10.4071/2380-4505-2018.1.000349" @default.
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