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• W2905247075 abstract "As the technology node continuously scales down, layout-dependent effects (LDEs) have been significantly affecting the threshold voltage and mobility of MOSFET transistors and then, in turn, the performance of analog integrated circuits. In this paper, we propose an LDE optimization methodology based on the evolutionary algorithm, which aims to protect analog circuits from the LDE-induced circuit performance degradation. With the aid of a fast analog layout retargeting scheme, our proposed optimization can evaluate the circuit performance with the consideration of detailed physical layouts, tune the device placement and transistor finger number, and modify the layout patterns for the LDE-aware circuit performance preservation. To accelerate the physical layout synthesis, our new retargeting process supports general device abstraction. The experimental results show that our proposed methodology can more effectively preserve analog and even RF circuit performance with higher efficiency than the alternative approaches." @default.
• W2905247075 created "2018-12-22" @default.
• W2905247075 creator A5051788465 @default.
• W2905247075 creator A5059448769 @default.
• W2905247075 date "2019-04-01" @default.
• W2905247075 modified "2023-09-27" @default.
• W2905247075 title "EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction" @default.
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• W2905247075 doi "https://doi.org/10.1109/tvlsi.2018.2883710" @default.
• W2905247075 hasPublicationYear "2019" @default.
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