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- W2908326617 abstract "Multi-core architectures using scratch pad memories are very attractive to execute embedded time-critical applications, because they offer a large computational power. However, ensuring that timing constraints are met on such platforms is challenging, because some hardware resources are shared between cores. When targeting the bus connecting cores and external memory, worst-case sharing scenarios are too pessimistic.This thesis propose strategies to reduce this pessimism. These strategies offer to both improve the accuracy of worst-case communication costs, and to exploit hardware parallel capacities by overlapping computations and communications. Moreover, fragmenting the latter allow to increase overlapping possibilities." @default.
- W2908326617 created "2019-01-11" @default.
- W2908326617 creator A5071661789 @default.
- W2908326617 date "2018-12-19" @default.
- W2908326617 modified "2023-09-23" @default.
- W2908326617 title "Minimising communication costs impact when scheduling real-time applications on multi-core architectures" @default.
- W2908326617 hasPublicationYear "2018" @default.
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