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- W2911156617 abstract "Routing is probably the most time-consuming stage in the FPGA compilation flow. While parallelization has the potential to reduce the routing time, load imbalance still arises in parallel routing process, resulting in the degradations of speedup and quality of results. Furthermore, when scaling the number of processing cores, load imbalance will become more severe in parallel routing. In this paper, we explore load balance-aware parallel routing to obtain significant speedup. To study load balance problem, we implement a basic MPI-based parallel routing framework on multi-core distributed-memory platform. This framework provides two dynamic partitioning algorithms and both of them can automatically maintain the load balance of parallel routing at runtime. The first is the heuristic algorithm and it is able to assign more nets to fast MPI processes by removing an equal number of nets from slow MPI processes. The second algorithm selects the re-partitioning of the nets for all the MPI processes at each iteration, further leading to a good load balance during parallel routing. The key idea of these two algorithms is to analyze the behaviours of previous iteration to guide the parallelization of next iteration. Results show that the effectiveness and efficiency of the two algorithms in multi-core distributed-memory parallel routing framework. Notably, our parallel router can achieve about 6x speedup on average using 8 MPI processes, comparing to the serial router. This is a 1.2x improvement over a state-of-the-art multi-core parallel router." @default.
- W2911156617 created "2019-01-25" @default.
- W2911156617 creator A5002840650 @default.
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- W2911156617 date "2018-10-01" @default.
- W2911156617 modified "2023-10-16" @default.
- W2911156617 title "Load Balance-Aware Multi-Core Parallel Routing for Large-Scale FPGAs" @default.
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- W2911156617 doi "https://doi.org/10.1109/iccd.2018.00095" @default.
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