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• W2911543181 abstract "On behalf of the organizing committee, we are delighted to welcome you to the 2016 ACM International Symposium on Physical Design (ISPD), held at Santa Rosa, California. Continuing the great tradition established by its twenty-four predecessors, which includes a series of five ACM/SIGDA Physical Design Workshops held intermittently in 1987-1996 and nineteen editions of ISPD in the current form since 1997, the 2016 ISPD provides a premier forum to present leading-edge research results, exchange ideas, and promote research on critical areas related to the physical design of VLSI and other related systems.The regular papers in the ISPD 2016 program were selected after a rigorous, month-long, doubleblind review process and a face-to-face meeting by the Technical Program Committee (TPC). The papers selected exhibit latest advancements in a variety of topics in physical design, including 3D integration, directed self-assembly, timing and clock optimization, reliability, adaptability, and the latest machine-learning based techniques for computer-aided design.The ISPD 2016 program is complemented by two keynote addresses, twelve invited talks and a tribute session, all of which are delivered by distinguished researchers from both industry and academia. Dr. Kevin Zhang, vice president at Intel Corporation, will talk about circuit design in nano-scale CMOS technologies in the Monday keynote speech. In the Tuesday keynote speech, Dr. Antun Domic, executive vice president at Synopsys, will present his observations on the physical design problems of the next decade. A commemorative session on Tuesday afternoon will pay tribute to Prof. Ralph Otten. His collaborators will share with us Dr. Otten's exceptional contributions to EDA research, including his pioneering effort in automated floorplanning and layout generation. There will be two special sessions and other invited talks interspersed with the presentations of the regular papers. The topics of the invited papers range from emerging technologies such as 3D ICs, directed self-assembly, neurosynaptic chips, sub-7nm designs, as well as the latest challenges in physical design of ICs and FPGAs.Since 2005, ISPD has organized highly competitive contests to promote and advance research in placement, global routing, clock network synthesis, discrete gate sizing, and detailed routingdriven placement. Unlike previous years' contests which are mostly on ASIC designs, this year's contest, organized by Xilinx, is on routability-driven FPGA placement. This is the first large-scale worldwide contest on FPGA placement optimizing towards important real-world objectives based on a realistic heterogeneous FPGA architecture. The contest evaluates the quality of an FPGA placement with an advanced commercial FPGA routing tool making the problem even more challenging and practical. It is expected to lead and motivate more research and contributions on FPGA physical design. Continuing the tradition of all the past contests, a new large-scale realworld benchmark suite for FPGA circuits based on an advanced heterogeneous FPGA architecture will be released in the ISPD website: http://www.ispd.cc" @default.
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• W2911543181 date "2016-04-03" @default.
• W2911543181 modified "2023-09-27" @default.
• W2911543181 title "Proceedings of the 2016 on International Symposium on Physical Design" @default.
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