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- W2912090469 abstract "The error-detecting latch (EDL), which consists of a latch and a transition detector (TD), is the key circuit to the success of timing-error resilient system design. In order to realize a truly variation-resilient design, it is imperative for the EDL to have low overheads in area, power, and leakage while maintaining robustness across all process/voltage/temperature (PVT) corners. This paper proposes a new EDL that achieves the lowest layout area and lowest active and leakage power consumption compared to all previous EDLs. The excellent features are due to a new TD, which requires a small number of transistors and whose logic style allows minimum transistor sizing even in the event of serious PVT variations. Post-layout simulations for various EDL designs in 28-nm CMOS show that the proposed EDL is 26% smaller in area, and achieves 4% and 33% reduction in active and leakage power consumption, respectively, in comparison to the state-of-the-art EDL. The proposed EDL also shows the best voltage scalability in achieving higher power and leakage reduction when operating at the minimum supply voltage (Vmin)." @default.
- W2912090469 created "2019-02-21" @default.
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- W2912090469 date "2018-09-01" @default.
- W2912090469 modified "2023-09-27" @default.
- W2912090469 title "A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs" @default.
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- W2912090469 doi "https://doi.org/10.1109/socc.2018.8618543" @default.
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