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- W2912094241 abstract "In advanced technology nodes, static power consumption dominates system power in applications that do not operate at high frequency. SRAM leakage is a major component of static power consumption of a SOC. In this paper, we propose a 81nW ultra low power error amplifier to control retention leakage of 4Mb SRAM array. The overall memory subsystem leakage power reduces by 50% from no retention case and 33% from the conventional retention solution at TT (25°C). At FNSP (140°C) leakage power reduces by 75% from no retention & 69% from conventional solution. Monte Carlo analysis shows the $3sigma$ variations are within guard band limits." @default.
- W2912094241 created "2019-02-21" @default.
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- W2912094241 date "2018-09-01" @default.
- W2912094241 modified "2023-10-18" @default.
- W2912094241 title "A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology" @default.
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- W2912094241 doi "https://doi.org/10.1109/socc.2018.8618569" @default.
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