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- W2912454911 abstract "This chapter presents a comprehensive study of the unique thermal behavior in monolithic 3D-ICs. In particular, the impact of the thin interlayer dielectric (ILD) between the device tiers on vertical thermal coupling is studied. In addition, a fast and accurate compact full-chip thermal analysis model based on nonlinear regression technique is developed. The model is extremely fast and highly accurate with an error of less than 5%. Next, the impact of power delivery network (PDN) on full-chip wirelength, routability, and power consumption in monolithic 3D-ICs is demonstrated. The results show that the full PDN worsens routing congestion more severely in monolithic 3D-ICs than in 2D designs due to the significant reduction in resources for 3D connections. The increase in signal wirelength translates into additional net switching power dissipation, which significantly contributes to the total power. The trade-offs between PDN and signal wirelength are more pronounced in monolithic 3D-ICs than 2D designs. Various PDN design optimization techniques for monolithic 3D-ICs are also discussed." @default.
- W2912454911 created "2019-02-21" @default.
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- W2912454911 date "2019-02-08" @default.
- W2912454911 modified "2023-10-12" @default.
- W2912454911 title "Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D‐ICs" @default.
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- W2912454911 doi "https://doi.org/10.1002/9783527697052.ch6" @default.
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