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- W2912505470 abstract "In this work, vertically stackedn-oxide-p transistor architecture is explored as 1T-DRAM. The moderately dopedp type region is utilized to modulate (i) state currents flowing through the top n-type conduction region, and (ii) Retention Time (RT) through charges stored at the back surface of p-type storage region. The creation of deeper potential well for charge storage inp-region is based on electrostatic doping effect (underneath Source/Drain regions and high gate workfunction values). ART of $sim$1 s and $sim$1 ms at gate lengths of 200 nm and 25 nm, respectively, at 85°C can be achieved. A low-$kappa$ (SiO 2 ) material for the separation of conduction and storage regions enables a higher RT due to lower electric field in the storage region." @default.
- W2912505470 created "2019-02-21" @default.
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- W2912505470 date "2018-10-01" @default.
- W2912505470 modified "2023-09-25" @default.
- W2912505470 title "1T DRAM with Vertically Stacked n-Oxide-p Architecture" @default.
- W2912505470 doi "https://doi.org/10.1109/s3s.2018.8640134" @default.
- W2912505470 hasPublicationYear "2018" @default.
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