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- W2912581040 abstract "In this paper, we present a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing any bit-dimension permutation into elementary bit-exchanges. Such decomposition is proven to achieve the theoretical minimum number of delays required for the permutation. This offers optimum solutions for multiple well-known problems in the literature that make use of bit-dimension permutations. This includes the design of permutation circuits for the fast Fourier transform, bit reversal, matrix transposition, stride permutations, and Viterbi decoders." @default.
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- W2912581040 date "2019-05-01" @default.
- W2912581040 modified "2023-10-09" @default.
- W2912581040 title "Optimum Circuits for Bit-Dimension Permutations" @default.
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- W2912581040 doi "https://doi.org/10.1109/tvlsi.2019.2892322" @default.
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