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- W2912603705 abstract "This dissertation applies new decision diagram representations to the synthesis of two-level AND-XOR circuits, and to the design verification of combinational circuits. These representations are modifications of the popular ordered binary decision diagram representation. First, exact equations for the worst-case sizes of ordered binary decision diagrams of general switching functions and completely symmetric functions are derived. Next, two-level AND-XOR circuits are synthesized by recursively reading product terms from a canonical representation of the three exclusive-or based expansions of a switching function. A comparison between AND-OR and AND-XOR based representations is made, and the minimized AND-XOR expressions are presented. Finally, combinational circuits are verified by comparing the canonical representations of gate-level circuit descriptions. To show that a canonical representation of practical size theoretically exists, a proof is presented of the existence of a polynomial size canonical representation for all VLSI-realizable switching functions. Constrained ordered binary decision diagrams are introduced as a step toward such a representation. These diagrams are used to represent and verify functions which cannot be represented with traditional ordered binary decision diagrams." @default.
- W2912603705 created "2019-02-21" @default.
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- W2912603705 date "1993-01-01" @default.
- W2912603705 modified "2023-09-26" @default.
- W2912603705 title "Applications of decision diagrams to design verification and logic synthesis" @default.
- W2912603705 hasPublicationYear "1993" @default.
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