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- W2912888224 abstract "By sidestepping the limitations at the memory interface, processing-in-memory (PIM) unlocks internally available memory bandwidth to the compute units on the memory side. This abundant bandwidth is conventionally utilized by highly-parallel throughput-oriented many-core style PIM architectures via offloading bandwidth-bound parallel tasks. However, it can be difficult to fully isolate these PIM-suitable tasks, and an offloaded program may include compute-bound sequential phases. These PIM-averse phases constitute a critical performance bottleneck for conventional many-core style PIM architectures. In this paper, we propose an analytical model for PIM execution that considers a program's bandwidth demand as well as its parallelism. Based on the proposed model, we make a case for an asymmetric PIM architecture that can mitigate the performance bottlenecks for PIM-averse phases while keeping the performance upside for PIM-suitable phases." @default.
- W2912888224 created "2019-02-21" @default.
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- W2912888224 date "2019-01-01" @default.
- W2912888224 modified "2023-09-27" @default.
- W2912888224 title "A Case For Asymmetric Processing in Memory" @default.
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- W2912888224 doi "https://doi.org/10.1109/lca.2019.2894800" @default.
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