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• W2912930041 abstract "We present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes by combining a Triple-Interlocked Cell (TICE) SRAM cell array and a Triple Modular Redundancy (TMR) voter. The TICE SRAM cells therein self-correct SEUs and DEUs. The TMR voter eliminates SETs. Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEUand DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells." @default.
• W2912930041 created "2019-02-21" @default.
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• W2912930041 date "2018-11-01" @default.
• W2912930041 modified "2023-09-23" @default.
• W2912930041 title "Single-Event-Transient Resilient Memory for DSP in Space Applications" @default.
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• W2912930041 doi "https://doi.org/10.1109/icdsp.2018.8631639" @default.
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