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- W2913777796 abstract "1-transistor and 2-transistor (1T/2T) SRAM are fabricated using 14 nm baseline foundry process without any process modifications. A bi-stable self-latch mechanism is established in a single transistor where its p-type body becomes electrically floating by reverse biased, buried depletion regions from adjacent n-wells. The bit cell operation and the disturb immunity are verified. A unit cell size of $0.039 mu mathrm{m}^{2}$ is achieved, offering >2x area reduction over 6T-SRAM and providing comparable power and performance." @default.
- W2913777796 created "2019-02-21" @default.
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- W2913777796 date "2018-12-01" @default.
- W2913777796 modified "2023-10-17" @default.
- W2913777796 title "A Bi-stable 1- /2-Transistor SRAM in 14 nm FinFET Technology for High Density / High Performance Embedded Applications" @default.
- W2913777796 doi "https://doi.org/10.1109/iedm.2018.8614555" @default.
- W2913777796 hasPublicationYear "2018" @default.
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