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- W2916004955 abstract "This paper presents a four-way row-splitting architecture for layered low-density parity-check (LDPC) decoder. Based on the proposed method, an efficient partially parallel pipelined QC-LDPC decoder is proposed. The synthesis results using TSMC 40-nm standard cell CMOS technology show that the proposed decoder achieves the maximum required throughput of 7.05 Gb/s and outperforms its predecessors in terms of area efficiency." @default.
- W2916004955 created "2019-03-02" @default.
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- W2916004955 date "2018-11-01" @default.
- W2916004955 modified "2023-10-16" @default.
- W2916004955 title "Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture" @default.
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- W2916004955 doi "https://doi.org/10.1109/isocc.2018.8649976" @default.
- W2916004955 hasPublicationYear "2018" @default.
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