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• W2916345759 abstract "A continuous-time second-order ΔΣ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter is high-pass shaped by intrinsic data-weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this paper. A prototype ADC is implemented in 65-nm CMOS and achieves 64.2-dB SNDR at a bandwidth of 2.5 MHz and a Schreier FoM of 158.2 dB. The ADC operates at 205 MHz and consumes 1 mW of power. The measured power supply rejection ratio is 56.2 dB." @default.
• W2916345759 created "2019-03-02" @default.
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• W2916345759 date "2019-07-01" @default.
• W2916345759 modified "2023-10-02" @default.
• W2916345759 title "Highly Digital Second-Order $DeltaSigma$ VCO ADC" @default.
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• W2916345759 doi "https://doi.org/10.1109/tcsi.2019.2898415" @default.
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