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- W2922326057 abstract "Advanced technology nodes are based on nFET and pFET fins, which are fabricated on the same Silicon level of the wafer. However, in a complimentary FET (CFET) technology the nFET and pFET devices are stacked on top of each other [1]. This provides a significant area reduction mainly driven by a simplified transistor terminal access and the removal of the lateral physical separation between the two transistors. The combination of the CFET with buried power rails can reduce the track height of the cells and the elusive 3 Track standard cell is seen to be a possibility." @default.
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- W2922326057 date "2019-03-20" @default.
- W2922326057 modified "2023-10-16" @default.
- W2922326057 title "CFET standard-cell design down to 3Track height for node 3nm and below" @default.
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- W2922326057 doi "https://doi.org/10.1117/12.2514571" @default.
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