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- W2922860067 abstract "3D stacked ICs package multiple, independently manufactured dies to reduce total system wire-length, improve timing, and reduce area and power. When designing stacked 3D-ICs, arises the question of the grain at which one should consider system partitioning to optimize the gains. This work uses known MAX-CUT graph partitioning algorithms to split designs from 42k up to 800k gates, with gates clustered from 8 and up to 32768 partitions. It has been found that with 2048 clusters, i.e. 20 to 400 gates per cluster depending on the design, a partitioning of the system allows on average to cut 35% of the nets that account for 73% of the total wire-length in 3D." @default.
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- W2922860067 date "2019-05-01" @default.
- W2922860067 modified "2023-09-23" @default.
- W2922860067 title "3D-Stacked Integrated Circuits: How Fine Should System Partitioning Be?" @default.
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- W2922860067 doi "https://doi.org/10.1109/iscas.2019.8702533" @default.
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