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- W2932430754 abstract "Abstract Integrated silicon photonic networks have attracted a lot of attention in the recent decades due to their potentials for low-power and high-bandwidth communications. However, these promising networks, as the future technology, are drastically susceptible to thermal fluctuations, which may paralyze wavelength-based operation of these networks. In this regard, precise addressing of thermally induced faults in optical networks-on-chip (ONoCs), as well as revealing practical methods to tackle this challenge will be a break-even point toward implementation of this technology. In this paper, thermal variation is investigated through analyzing on-chip power distribution, which is addressed by power profile of SPEC 2006 benchmark applications. Based on these assessments, herein we propose a low-power thermal-resilient optical network-on-chip (The-RONoC) architecture that significantly mitigates routing faults in ONoC. Utilizing a corrective unit in this architecture, 50% of the thermally induced switching faults are recovered with the cost of less than 2% area overhead. In addition, up to 42% performance improvement is achieved through this architecture in comparison to the basic architecture. Finally, we explore scalability of The-RONoC based on formal SNR analysis, as well as power consumption and the probability of optical transmission speed-up." @default.
- W2932430754 created "2019-04-11" @default.
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- W2932430754 date "2019-06-01" @default.
- W2932430754 modified "2023-09-25" @default.
- W2932430754 title "Low-overhead thermally resilient optical network-on-chip architecture" @default.
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- W2932430754 doi "https://doi.org/10.1016/j.nancom.2019.03.001" @default.
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