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- W2938706722 abstract "One of the most important building blocks in analog to digital converter (ADC) is sample and hold (S/H) circuit. The function of this circuit is to hold the input voltage until ADC completes the conversion process. The accuracy of S/H circuit is limited by channel charge injection and clock feedthrough. In this paper, a new method to minimize hold error in CMOS TG switch S/H circuit using feedforward neural network as function approximation is proposed. The basic idea of the proposed method is to minimize hold error by adjusting the width of NMOS transistor $pmb{(W_{n})}$ and PMOS transistor $pmb{(W_{p})}$ in CMOS switch numerically using a trained neural network. The performance of the proposed method is evaluated using HSPICE with 180 nm CMOS standard process. As a result, HSPICE simulation verified that hold error produced by S/H circuit whose $W_{p}$ and $W_{n}$ are generated using the minimization method is mostly zero. The maximum and average hold error is $pmb{20 mu} mathbf{V}$ and $pmb{2 mu} mathbf{V}$ , respectively." @default.
- W2938706722 created "2019-04-25" @default.
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- W2938706722 date "2018-10-01" @default.
- W2938706722 modified "2023-09-25" @default.
- W2938706722 title "Hold Error Minimization Method on S/H Circuit Using Feedforward Neural Network as a Function Approximation" @default.
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- W2938706722 doi "https://doi.org/10.1109/eeccis.2018.8692978" @default.
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