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- W2940470334 abstract "In this paper we demonstrate how artificial intelligence approaches such as machine learning presents an efficient technique for testing key aspects of EDA software and for validating its quality of results, especially in the context of FPGA architectures. To do so, we describe how we apply a machine learning algorithm, namely random forest, to the case of testing and quality verification of an AWE-based delay estimation algorithm when applied to FPGA routing nets. The proposed testing application uses a machine learning model to identify potential net delay calculation errors, which then are flagged for an in-depth targeted verification. The ML model is trained using SPICE, a golden delay calculation reference. The ML features are derived from the regularity and repeatability found in FPGAs. Results obtained on a 28nm FPGA testing data set are very promising, and show higher than 97% detection rate of randomly injected errors." @default.
- W2940470334 created "2019-05-03" @default.
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- W2940470334 date "2019-03-01" @default.
- W2940470334 modified "2023-10-17" @default.
- W2940470334 title "An Artificial Intelligence Approach to EDA Software Testing: Application to Net Delay Algorithms in FPGAs" @default.
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- W2940470334 doi "https://doi.org/10.1109/isqed.2019.8697652" @default.
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