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- W2940559878 abstract "This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulated with 65nm techonology, 1.2V and tsmc foundary model files" @default.
- W2940559878 created "2019-05-03" @default.
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- W2940559878 date "2018-04-03" @default.
- W2940559878 modified "2023-10-14" @default.
- W2940559878 title "10Ghz Charge Pump PLL for Low Jitter Applica-tions" @default.
- W2940559878 doi "https://doi.org/10.14419/ijet.v7i2.12.11349" @default.
- W2940559878 hasPublicationYear "2018" @default.
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