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• W2941750552 abstract "High level synthesis (HLS) is often employed as a frequently called kernel in design space exploration (DSE). Therefore, its nontrivial runtime becomes a bottleneck that prevents extensive solution search in DSE. In this work, we develop a mapping-based HLS technique that is fast and friendly to local incremental changes. It exploits the static-single assignment (SSA)-form intermediate representation (IR), starts with direct mapping from the IR to a fully pipelined circuit and performs incremental resource sharing in an iterative manner, which then alters the fully pipelined circuit to a partially pipelined or nonpipelined circuit. An algorithm is also proposed for automatic synthesis of pipeline interlocks to avoid structural hazards incurred by resource conflicts. Experimental results show that the proposed method is fast without loss of circuit performance in terms of throughput." @default.
• W2941750552 created "2019-05-03" @default.
• W2941750552 creator A5008868985 @default.
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• W2941750552 date "2019-03-01" @default.
• W2941750552 modified "2023-10-03" @default.
• W2941750552 title "Fast Mapping-Based High-Level Synthesis of Pipelined Circuits" @default.
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• W2941750552 doi "https://doi.org/10.1109/isqed.2019.8697596" @default.
• W2941750552 hasPublicationYear "2019" @default.
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