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- W2944108850 abstract "A 10-bit SAR ADC was designed in a 130 nm CMOS process. The reference voltage generator in the ADC is made with an array of 25 unit capacitors, in comparison to binary-weighted SAR ADCs, which would use 1024 unit capacitors. The capacitor array is controlled using a state machine whose logic was determined and automatically generated using a recursive backtracking algorithm.Schematic-level simulation results for the ADC predict an effective number of bits (ENOB) of 9.39, worst case integral non-linearity (INL) and differential non-linearity (DNL) of 1.15 and 1 least significant bit (LSB), respectively, and average power consumption of 1.65 µW at 10 kSps. The Walden figure of merit is calculated to be 246 fJ/conv-step. The core layout area is 0.458 mm^2." @default.
- W2944108850 created "2019-05-16" @default.
- W2944108850 creator A5084613942 @default.
- W2944108850 date "2018-11-13" @default.
- W2944108850 modified "2023-09-27" @default.
- W2944108850 title "Backtracking Algorithm-Aided Design of a 10-Bit SAR ADC" @default.
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- W2944108850 doi "https://doi.org/10.22215/etd/2018-13221" @default.
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