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- W2945290399 abstract "The complexity level of hardware design has increased extensively, and consequently it became subject of errors. That's why it is extremely important to verify the correctness of designs, especially in critical systems like those of security. The problem is that the typical Hardware Description Languages (HDLs) like VHDL and Verilog are made mostly for description and simulation purposes; however, the simulation is insufficient validation technique in complex designs such as the cryptographic circuits. Thus, formal verification has become an important technique towards establishing the correctness of hardware designs; nonetheless it still faces many challenges; which make it a worth-while research problem. This paper presents an approach to formally verify the cryptographic circuits. It consists of using a purely functional framework namely Haskell to describe both the behavioral and structural descriptions. In addition, such approach relies on the use of hierarchy and modularity techniques in order to reduce the design complexity, and hence simplify the verification task. Last but not least we use Lava which is an HDL embedded into Haskell that allows checking automatically the safety and equivalence properties of circuits in several ways. To show the potential features of the proposed approach, we applied it to the Data Encryption Standard (DES) circuit, which is a symmetric block cipher. Thereafter, a methodological design approach for the verification of the design implementation against the specification is presented." @default.
- W2945290399 created "2019-05-29" @default.
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- W2945290399 date "2019-01-01" @default.
- W2945290399 modified "2023-09-23" @default.
- W2945290399 title "Formal verification of cryptographic circuits" @default.
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- W2945290399 doi "https://doi.org/10.1145/3320326.3320367" @default.
- W2945290399 hasPublicationYear "2019" @default.
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