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• W2945802254 abstract "A dither-based background calibration with data-weighted averaging logic to correct capacitor mismatch and inter-stage gain error in pipelined noise shaping successive approximation register ADCs is proposed. By injecting the dither signal in the background, the inter-stage gain is obtained. Besides, the data-weighted averaging logic is adopted to dissipate harmonics caused by the mismatch of capacitors. Owing to the effective combination of the two methods, there is no need to detect the conditions of injecting the dither signal. As a result, the calibration requires simple logic and adds little analogue overhead." @default.
• W2945802254 created "2019-05-29" @default.
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• W2945802254 date "2019-09-01" @default.
• W2945802254 modified "2023-09-23" @default.
• W2945802254 title "Dither‐based background calibration of capacitor mismatch and gain error in pipelined noise shaping successive approximation register ADCs" @default.
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• W2945802254 doi "https://doi.org/10.1049/el.2019.0872" @default.
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